Logic cell arrays, such as, for example, reconfigurable logic cell arrays include, as particular types, systolic arrays, neuronal networks, multi-processor systems, processors having a number of arithmetic-logic units, and/or logic cells and/or communicative/peripheral cells (I/O), networking and/or network chips, such as crossbar switches, as well as FPGA, DPGA, Xputer, Chameleon chips, etc. The following patents commonly assigned to the assignee of the present application describe logic cell arrays and are incorporated by reference in their entirety: German Patent No. 44 16 881; German Patent No. 197 81 412; German Patent No. 197 81 483; German Patent No. 196 54 846, German Patent No. 196 54 593; German Patent No. 197 04 044; German Patent No. 198 80 129, German Patent No. 198 61 088, German Patent No. 199 80 312; International Patent Application No. PCT/DE 00/01869; German Patent No. 100 36 627, German Patent No. 100 28 397, German Patent No. 101 10 530, German Patent No. 101 11 014, International Patent Application No. PCT/EP 00/10516, and European Patent No. 01 102 674. According to their wide variety, logic cells are herein defined as any cells that contain logic, arithmetic, switches, memory, or peripherals.
In systems such as those previously cited, there are approaches that enable in efficient processing of data which may be implemented in hardware architectures. There nevertheless exists in practical implementations the need to optimize designs, which, in particular, can be structured in a space-saving manner on a wafer and/or can be operated in an energy-saving manner. Additionally, it is desirable to find especially advantageous kinds of operation.
One of the difficulties with conventional systems is that a large number of cells have to communicate with each other. The communication may be required in order to pass the data to be processed from one cell to another. This is the case, for example, if a cell is supposed to further process the results from another cell, e.g., by linking of the result obtained there to results obtained from one or more other cells. Furthermore, communication may be required to transmit status signals.
Busses for transmitting signals to one of a number of possible receivers have been used in this context. Busses are bundles of wires, the number of wires typically being determined from the number of bits to be transmitted together, that is, typically in parallel, plus in some cases a series of status lines.
With conventional simple busses, as are used, for example, in PC's for the communication of plug-in boards with the CPU and/or with each other, the bus lines may be routed to all receivers, and then appropriate control signals transmitted along with them, that is, addressing, ensures that only those receivers respond that are supposed to receive the data. Such a system becomes problematic when a great many communicating units need access to the bus or busses. This is because the communication of data must wait, if necessary, until the bus has been released by other units and/or time-slice solutions must be implemented that grant a transmitting unit only a certain transmission time, which as a rule is independent of whether all data has been transmitted in this time, which might also make it necessary to use a number of time slices for the data transmission. For example, this approach is practiced in systems like the token ring network. In systems like logic cell arrays, in which very rapid communication is desired in order to ensure high data processing speeds, this is an undesirable solution.
It has also been proposed that the busses be segmented. If, for example, in a series of logic cells several units to be connected to each other are disposed close together in pairs, a bus line that passes along all units and consequently is long may be separated by means of switches in order to form several subbus systems. In this context, each segment, like the entire bus, comprises the required number of parallel data lines and the additionally required protocol lines; the communication of a pair of logic cells that are disposed close together does not disrupt the communication of another pair that are disposed close together. In this way, the data rate that is transmitted via the bus system may be substantially increased.
However, this system may not work well when integrated on semiconductor chips, such as in CMOS technology, where the structure is typically complex and the operation is energy inefficient.